RISC-V

RISC-V

Created by Team Register //

Mon 18 Oct 2021

RISC-V is an open royalty-free instruction set architecture for general purpose CPU cores. RISC-V International sets and publishes the specification of this architecture, and chip designers are free to implement it in their components.

Alibaba's research arm promises server-class RISC-V processor due this year

And teases a laptop to show off its current silicon – running the open edition of Huawei’s CentOS spinout

Systems20 Mar 2024 | 8

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Tenstorrent's Blackhole chips boast 768 RISC-V cores and almost as many FLOPS

SiFive offers potential Neoverse N2 rival – the P870-D RISC-V core for datacenters

Akeana debuts RISC-V CPU designs on $100M budget, longs for an Arm wrestle

Raspberry Pi Pico 2 lands with (drum roll) RISC-V cores

Faulty instructions in Alibaba's T-Head C910 RISC-V CPUs blow away all security

Linux kernel 6.10 arrives with punched-up hardware support

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World's first RISC-V laptop with Ubuntu preloaded touts AI smarts and octa-core chip

Why RISC-V must get its messaging right on open standard vs open source

Google pulls RISC-V support from generic Android kernel

US government reportedly ponders crimping China's use of RISC-V

RISC-V AI chip upstart Rivos plans to undercut Nvidia, helped by a quarter-billion in VC lucre

SiFive is back with another 64-bit RISC-V dev board – hopefully

Imagination licenses RISC-V CPU cores for smart TVs, IoT, embedded stuff

Chinese schools testing 10,000 locally made RISC-V-ish PCs

Scaleway shows off its new RISC-V devices at Kubecon

RISC-V PCIe 5 SSD controller for the rest of us hits 14GB/s

Alibaba's research arm promises server-class RISC-V processor due this year

Leaked docs hint Google may use SiFive RISC-V cores in next-gen TPUs

French cloud Scaleway starts renting Alibaba's RISC-V SoC

India’s homebrew RISC-V CPU goes on sale in new development board

MIPS snags top SiFive brains to amp up RISC-V business

Ventana bumps performance on Veyron RISC-V silicon to surely speed up servers

Synopsys joins RISC-V party with trio of embedded core designs

Hardware hacker: Walling off China from RISC-V ain't such a great idea, Mr President

Arm grabs a slice of Raspberry Pi to sweeten relationship with IoT devs

Google formally gets to work on Android on RISC-V

RISC-V champ SiFive confirms it's laying off 1 in 5 workers

Hot fuzz: Cascade finds dozens of RISC-V chip bugs using random data storm

India courts IBM, Intel, and Tower for chip partnerships - all in one day

Google and Qualcomm to bring RISC-V to the wrist in next-gen wearable platform

Latest SiFive RISC-V cores aim to boost performance, accelerate AI workloads

RISC-V org claims export restrictions would stifle innovation

Boffins propose RISC-V microcontroller to power cubesats

Samsung to fab chips for RISC-V processor world's Tenstorrent

Intel spices up its FPGA game with open source and RISC-V freebies

China's top RISC-V players form patent alliance

Big chip players join forces to form another RISC-V venture

Linux Foundation and pals – including Intel – back software ecosystem around RISC-V

Linux 6.3 debuts after 'nice, controlled release cycle'

India to ride the AI rocket responsibly, rather than regulate

Chinese web giant Baidu backs RISC-V for the datacenter

China accelerates drive for scientific self-sufficiency

The Balthazar laptop: An all-European RISC-V Free Hardware computer

Xen hypervisor port to RISC-V moving – slowly, but moving

Could RISC-V become a force in high performance computing?

After less than half a year, Intel quietly kills RISC-V dev environment

Qualcomm talks up RISC-V, roasts 'legacy architecture' amid war with Arm

Ventana targets hyperscalers with customizable RISC-V server chip

Brit chip company picks RISC-V for next-gen microcontrollers

Alibaba, Tencent enlisted to help sanction-weary China build RISC-V chips

Ubuntu continues expanding RISC-V support – now, the $17 Sipeed LicheeRV

Chinese city of Shenzhen offers free money to boost chip industry

China may prove Arm wrong about RISC-V's role in the datacenter

SiFive RISC-V cores picked for Google AI compute nodes

Arm execs: We respect RISC-V but it's not a rival in the datacenter

SiFive RISC-V CPU cores to power NASA's next spaceflight computer

Alibaba Cloud launches RISC-V developer platform for edge SoCs

One of the first RISC-V laptops may ship in September, has an NFT hook

RISC-V International emits more open CPU specs

Will this be one of the world's first RISC-V laptops?

GNU Compiler Collection adds support for China's LoongArch CPU family

The ‘substantial contributions’ Intel has promised to boost RISC-V adoption

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